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Languguage OS II Version 10-94 (Knowledge Media)(1994).ISO
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RESETV.LST
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1991-03-01
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Motorola Family Assembler BETA TEST VERSION (2.1.5 ) Fri Mar 01 13:32:03 1991
abs. rel. LC obj. code source line
---- ---- ---- --------- -----------
1 1 |
2 2 |** Set checksum at "CHECKVAL" below! **
3 3 |
4 4 | TTL Reset Vector and Code Size
5 5 | OPT P=68332
6 6 |******************************************************************************
7 7 |** Exported portion ***
8 8 |*V****************************************************************************
9 9 |*** ***
10 10 |*** MODULE: ***
11 11 |*** RESETV - This module contains the reset vector for the system. ***
12 12 |*** It also includes a longword that contains the size of ***
13 13 |*** the code segment in bytes and all of the user custom- ***
14 14 |*** ization parameters. ***
15 15 |*** ***
16 16 |*** ENVIRONMENT: ***
17 17 |*** M68300 BCC EVM system ***
18 18 |*** ***
19 19 |*** LANGUAGE: ***
20 20 |*** M68MASM for MS-DOS MC68332 assembly language relocatable module ***
21 21 |*** ***
22 22 |*** SUMMARY OF CONTENTS: ***
23 23 |*** <will be linked to start at $E0000 for BCC> ***
24 24 |*** System reset vector. ***
25 25 |*** Code segment size. ***
26 26 |*** User customization parameters. ***
27 27 |*** ***
28 28 |*** NOTES: ***
29 29 |*** 1. Source equivalent copy of CPU32Bug parameter area for Motorola ***
30 30 |*** FREEWARE Bulletin Board System (BBS) to produce object ***
31 31 |*** equivalent code. See REVISION HISTORY below for version nbr. ***
32 32 |*** 2. This source code can be freely used at no cost/obligation, ***
33 33 |*** i.e. it is PUBLIC DOMAIN software. Please report any errors/ ***
34 34 |*** additions to the SYSOP of the Motorola FREEWARE BBS. ***
35 35 |*** 3. Parameters which reference linker symbols (XREF/XDEF) will ***
36 36 |*** not be defined until link time, so the obj. code listed here ***
37 37 |*** will not match the actual EPROM code. ***
38 38 |*** ***
39 39 |*^****************************************************************************
40 40 |*** INTERNAL PORTION OF THE MODULE HEADER ***
41 41 |******************************************************************************
42 42 |*** ***
43 43 |*** REVISION HISTORY (add changes to the top): ***
44 44 |*** ***
45 45 |*** DATE AUTHOR CHANGES ***
46 46 |*** ---------- --------------- ------------------------------------- ***
47 47 |*** 03/01/91 Peter S. Gilmour Compatible with CPU32Bug version 1.00. ***
48 48 |*** 05/02/90 Peter S. Gilmour Compatible with 332Bug version 1.02. ***
49 49 |*** 01/16/90 Peter S. Gilmour Initial version port to MS_DOS based ***
50 50 |*** M68MASM from original source code. ***
51 51 |*** Compatible with 332Bug version 1.01. ***
52 52 |*** ***
53 53 |******************************************************************************
54 54 |
55 55 |*** ***
56 56 |*** XDEFS: ***
57 57 |*** ***
58 58 | XDEF ORIGIN Start of program space
59 59 | XDEF CODESIZE Size of program space in bytes
60 60 | XDEF CHECKSUM Permit access by confidence test
61 61 |* Old CSn base addr reg. values
62 62 | XDEF .CSBAR0,.CSBAR1,.CSBAR2,.CSBAR3,.CSBAR4,.CSBAR5
63 63 | XDEF .CSBAR6,.CSBAR7,.CSBAR8,.CSBAR9,.CSBAR10
64 64 |* Old CSn base addr reg. values
65 65 | XDEF .CSOR0,.CSOR1,.CSOR2,.CSOR3,.CSOR4,.CSOR5
66 66 | XDEF .CSOR6,.CSOR7,.CSOR8,.CSOR9,.CSOR10
67 67 |* Common CSBOOT values
68 68 | XDEF .CSBARBT Old/new CSBOOT base addr reg. value
69 69 | XDEF .CSORBT Old/new CSBOOT option reg. value
70 70 |* New CSn base addr reg. values
71 71 | XDEF CSBAR0$,CSBAR1$,CSBAR2$,CSBAR3$,CSBAR4$,CSBAR5$
72 72 | XDEF CSBAR6$,CSBAR7$,CSBAR8$,CSBAR9$,CSBAR10$
73 73 |* New CSn base addr reg. values
74 74 | XDEF CSOR0$,CSOR1$,CSOR2$,CSOR3$,CSOR4$,CSOR5$
75 75 | XDEF CSOR6$,CSOR7$,CSOR8$,CSOR9$,CSOR10$
76 76 |
77 77 | XDEF MCR_OR MCR bits to add at power-on
78 78 | XDEF MCR_AND MCR bits to delete at power-on
79 79 | XDEF .PICR Periodic interrupt control reg. value
80 80 | XDEF .PITR Periodic interrupt timer reg. value
81 81 | XDEF RB_SP Rom Auto Boot SP location in ROM
82 82 | XDEF RB_PC Rom Auto Boot PC location in ROM
83 83 | XDEF CONSCI Console default SCI parameter table
84 84 | XDEF .PARMS SCI parameter definition
85 85 | XDEF .BAUD SCI baud rate value
86 86 | XDEF .PARITY SCI parity value
87 87 | XDEF .DATA SCI nbr. data bits value
88 88 | XDEF .STOP SCI nbr. stop bits value
89 89 | XDEF .XON_ENB SCI XON/XOFF enable value
90 90 | XDEF .XON SCI XON value
91 91 | XDEF .XOFF SCI XOFF value
92 92 | XDEF SYPCR_OR SYPCR bits to add at power-on
93 93 | XDEF SYPCR_AND SYPCR bits to delete at power-on
94 94 | XDEF FEXTAL External clock frequency (in Hz)
95 95 | XDEF FCRYSTAL Crystal frequency (in Hz)
96 96 | XDEF PWR_ON Start of Power on branch vectors
97 97 | XDEF PWR_TBL1 Init. Table #1 Power on branch vector
98 98 | XDEF PWR_INI MCU init. Power on branch vector
99 99 | XDEF PWR_TBL2 Init. Table #2 Power on branch vector
100 100 | XDEF PWR_TTL Sign on title Power on branch vector
101 101 | XDEF PWR_TST Self-test Power on branch vector
102 102 | XDEF PWR_GO System Go Power on branch vector
103 103 | XDEF INITTBL Initialization Table
104 104 | XDEF INITTBLE Initialization Table end
105 105 | XDEF SIGNON Offset to system sign on message text
106 106 |*** ***
107 107 |*** XREFS: ***
108 108 |*** ***
109 109 | XREF CONFTST Confidence test entry point
110 110 | XREF SYSINIT Start of program (system init.)
111 111 | XREF INIT_CS MCU initialization (chip selects, etc.
112 112 | XREF INIT_T1 Table #1 Initialization
113 113 | XREF INIT_T2 Table #2 Initialization
114 114 | XREF MEMPAGE 16 Megabyte page
115 115 |*** ***
116 116 |*** Local macros: ***
117 117 |*** ***
118 118 |VECTOR MACRO ! SETUP VECTOR SPACE
119 119 |SECTD SET 0 ! DEFINE DATA SECTION
120 120 |SECTP SET 8 ! DEFINE PROGRAM SECTION
121 121 | SECTION SECTP ! PUT USER INTO PROG. SECTION
122 122 | ENDM !
123 123 |
124 124 |***
125 125 |*** Local equates:
126 126 |***
127 127 0000 000D |CR EQU $0D ASCII carriage return
128 128 0000 000A |LF EQU $0A ASCII line feed
129 129 0000 0020 |SPACE EQU $20 ASCII space
130 130 |
131 131 |*
132 132 |* For M68300 BCC and PFB.
133 133 |*
134 134 |* NOTE: Unused upper address lines are specified as 1's so ABSOLUTE SHORT
135 135 |* addressing (sign extension) can be used.
136 136 |*
137 137 0000 2700 |SR_VAL EQU $2700 status register initial value.
138 138 |
139 139 0000 0000 |RAM_BASE EQU $0 BCC RAM base address
140 140 0001 0000 |RAM_SIZE EQU $10000 BCC RAM size (bytes)
141 141 000E 0000 |ROM1_BASE EQU $E0000 BCC EPROM base address
142 142 0002 0000 |ROM1_SIZE EQU $20000 BCC EPROM size (bytes)
143 143 0004 0000 |IRAM_BASE EQU $40000
144 144 FFFF E800 |FPCP_BASE EQU $FFFFE800 PFB MC68881/MC6882 base address
145 145 |* . (Floating Point Co-Processor)
146 146 0000 8000 |FCRYSTVAL EQU 32768 Crystal frequency (in Hz)
147 147 FFFF F000 |HI_BASE EQU $FFFFF000 CPU32 module (registers) base high addr
148 148 |* . This is the default used at power-up!
149 149 007F F000 |LO_BASE EQU $007FF000 CPU32 module (registers) base low addr
150 150 0000 0A00 |SIM EQU $A00 CPU32 System Integration Module base addr
151 151 0000 0B00 |RAMCR EQU $B00 CPU32 RAM Control Module base offset
152 152 0000 0C00 |QSM EQU $C00 CPU32 Queued Serial Module base offset
153 153 FFFF F800 |AUTO_BASE EQU $FFFFF800 Autovector base address
154 154 |
155 155 |* Define bits for Power Up Status (PWRSTATUS) flag:
156 156 0000 001F |EXTAL_BIT EQU 31 External Clock flag bit: 0= off (VCO)
157 157 0000 001E |CHKSUM_BIT EQU 30 Checksum not pgm'd yet bit: 0= pgm'd
158 158 |
159 159 0000 0000 |LOCALRAM EQU RAM_BASE base of local RAM
160 160 0000 4000 |SYSRAMSZ EQU $00004000 size of local RAM (for system use)
161 161 0001 0000 |LCLRAMMX EQU RAM_SIZE max size of local RAM (for M68332 BCC)
162 162 0000 4000 |USRRAM EQU LOCALRAM+SYSRAMSZ base of user RAM
163 163 0000 C000 |USRRAMSZ EQU LCLRAMMX-SYSRAMSZ size of user RAM
164 164 0000 0000 |RAMSTART EQU LOCALRAM alias for base of local RAM
165 165 |
166 166 000E 0000 |LOCALROM EQU ROM1_BASE base of local ROM (use PC rel refs!)
167 167 0001 0000 |LCLROMSZ EQU $00010000 size of local ROM used by 332Bug
168 168 0000 00FF |ROMUNPGM EQU $FF unprogrammed state of a byte of EPROM
169 169 0000 00FF |FILL.1 EQU ROMUNPGM fill value for 1 byte = BYTE
170 170 0000 FFFF |FILL.2 EQU FILL.1<<8+FILL.1 fill value for 2 bytes= WORD
171 171 FFFF FFFF |FILL.4 EQU FILL.2<<16+FILL.2 fill value for 4 bytes= LONG WORD
172 172 |
173 173 0001 0000 |RAM2_BASE EQU LOCALRAM+LCLRAMMX Next RAM base address
174 174 0010 0000 |ROM2_BASE EQU ROM1_BASE+ROM1_SIZE Next ROM base address
175 175 |
176 176 0000 0400 |VECTSIZ EQU $400 Vector table size
177 177 0000 1000 |USERLEN EQU $1000 user space reserved
178 178 0000 4000 |MEMINC EQU $4000 memory increment for 130's or EVM's
179 179 0000 2BFC |STKLEN EQU MEMINC-USERLEN-VECTSIZ-4 size of bug/diag stack + static vars
180 180 |
181 181 |*
182 182 |* Interrupt levels & vectors
183 183 |*
184 184 0000 0007 |ABORTLVL EQU 7 abort level
185 185 0000 001F |ABORTVEC EQU 31 abort vector
186 186 0000 0007 |ACFAILVL EQU 7 AC-Fail level
187 187 0000 0041 |ACFAILVC EQU 65 AC-Fail vector
188 188 0000 0006 |TIMERLVL EQU 6 timer level: M68332 periodic int. timer
189 189 0000 0042 |TIMERVEC EQU 66 timer vector
190 190 |
191 191 |*
192 192 |* Setup Base Addresses:
193 193 |* 1. A31-A24 must= 0 (MC68332 only uses A0-A23; rest are unused!)
194 194 |* 2. A10-A0 must= 0 (for Base Address Register usage).
195 195 |*
196 196 00FF F800 |ADDRMASK EQU $00FFF800 Address mask (24-bits, A10-A0= 0)
197 197 0000 0000 |RAM EQU RAM_BASE&ADDRMASK Setup Base Addresses
198 198 000E 0000 |ROM EQU ROM1_BASE&ADDRMASK Setup Base Addresses
199 199 0001 0000 |RAM2 EQU RAM2_BASE&ADDRMASK Setup Base Addresses
200 200 0010 0000 |ROM2 EQU ROM2_BASE&ADDRMASK Setup Base Addresses
201 201 00FF E800 |FPCP EQU FPCP_BASE&ADDRMASK Setup Base Addresses
202 202 0004 0000 |IRAM EQU IRAM_BASE&ADDRMASK Setup Base Addresses
203 203 00FF F800 |AVEC_7 EQU AUTO_BASE&ADDRMASK Setup Base Addresses
204 204 |
205 205 0000 0000 |CSBAR_XX EQU $0000 Reset (unused) value for CSBARn
206 206 0000 0000 |CSOR_XX EQU $0000 Reset (unused) value for CSORn
207 207 |
208 208 |*
209 209 |* Option Register Equates (CSORBT, CSORn):
210 210 |*
211 211 0000 0000 |B2K EQU 0 2K block size
212 212 0000 0001 |B8K EQU 1 8K block size
213 213 0000 0002 |B16K EQU 2 16K block size
214 214 0000 0003 |B64K EQU 3 64K block size
215 215 0000 0004 |B128K EQU 4 128K block size
216 216 0000 0005 |B256K EQU 5 256K block size
217 217 0000 0006 |B512K EQU 6 512K block size
218 218 0000 0007 |B1M EQU 7 1MB block size
219 219 0000 0000 |ASYNC EQU $0000 Asynchronous mode
220 220 0000 8000 |SYNC EQU $8000 Synchronous mode
221 221 0000 4000 |CS_UPPB EQU 2*$2000 Upper byte
222 222 0000 2000 |CS_LOWB EQU 1*$2000 Lower byte
223 223 0000 6000 |CS_BOTHB EQU 3*$2000 Both bytes (upper or lower)
224 224 0000 0800 |CS_R EQU 1*$800 Read
225 225 0000 1000 |CS_W EQU 2*$800 Write
226 226 0000 1800 |CS_RW EQU 3*$800 Read or write
227 227 0000 0000 |CS_AS EQU 0*$400 Address Strobe (AS*)
228 228 0000 0400 |CS_DS EQU 1*$400 Data Strobe (DS*)
229 229 0000 000E |CS_FAST EQU 14 Fast termination DSACK*
230 230 0000 000F |CS_EXT EQU 15 External termination DSACK*
231 231 0000 0040 |CS_WAIT EQU 1*$40 Wait cycles for DSACK*
232 232 0000 0000 |CS_CSP EQU 0*$10 CPU space
233 233 0000 0010 |CS_USP EQU 1*$10 User space
234 234 0000 0020 |CS_SSP EQU 2*$10 Supervisor space
235 235 0000 0030 |CS_SUSP EQU 3*$10 Supervisor/User space
236 236 0000 0002 |CS_LVL EQU 1*$2 Interrupt priority level
237 237 0000 0001 |CS_AVEC EQU 1 Autovector enable
238 238 |
239 239 |
240 240 |* Select value for checksum below:
241 241 |* - place "*" in front of the one you DON'T want assembled
242 242 |*
243 243 |*CHECKVAL EQU FILL.2 Checksum value for debugging
244 244 0000 3033 |CHECKVAL EQU $3033 Checksum value for finished product
245 245 |* . - must not be same as FILL.2!
246 246 |* The actual value of the checksum word is not known at the time
247 247 |* that this file is assembled or linked. However, an "intelligent"
248 248 |* checksum method is used whereby the program tells the user what
249 249 |* the checksum should be if the checksum hasn't been programmed yet!
250 250 |* Make the change, re-make the program, and blow new EPROM.
251 251 |*
252 252 |* The checksum word consists of two bytes that are placed at offset
253 253 |* locations $0E-0F in the Bug EPROM and is used during execution of
254 254 |* the confidence check to validate the EPROM contents.
255 255 |*
256 256 |
257 257 |********************************
258 258 |** Configuration Parameters **
259 259 |********************************
260 260 |* DO NOT ALTER! Must match with user documentation!
261 261 |*
262 262 | VECTOR
263 1m 0000 0000 +SECTD SET 0 ! DEFINE DATA SECTION
264 2m 0000 0008 +SECTP SET 8 ! DEFINE PROGRAM SECTION
265 3m 0000 + SECTION SECTP ! PUT USER INTO PROG. SECTION
266 263 |*
267 264 0000 0000 |ORIGIN EQU *
268 265 0000 0000 2FFC |PWR_SSP DC.L LOCALRAM+VECTSIZ+STKLEN Init. SSP = below user ram
269 266 0004 0000 0090 |PWR_PC DC.L PWR_ON Init. PC = power on branch vector
270 267 |**
271 268 0008 0002 0000 |CODESIZE DC.L ROM1_SIZE Set Code Size (in bytes)
272 269 000C 20 |SRECMAX DC.B 32 Maximum # data bytes to put in S-records
273 270 |* . Valid range= 1..250 (includes S3,S7)
274 271 |* . (used by DU command)
275 272 000D FF |CHECKALT DC.B FILL.1 -- reserved -- (alternate checksum)
276 273 000E 3033 |CHECKSUM DC.W CHECKVAL Allocate space for checksum word
277 274 |* . If CHECKVAL = FILL.2, then change
278 275 |* . value of CHECKALT location!
279 276 |
280 277 |* NOTE: "/256" is used in the Chip Select Tables below to shift address bits
281 278 |* A23-A11 to bit positions B15-B3 (23-15= 8 bits = 256) for use in the
282 279 |* SIM Base Address Registers.
283 280 |
284 281 |*----------------------------------------------------------------------------
285 282 |* Old Chip Select Table: (Rev. A BCC + Rev. A PFB)
286 283 |*
287 284 0010 0003 |.CSBAR0 DC.W RAM/256+B64K CS0 base & option register values
288 285 0012 5830 |.CSOR0 DC.W 0*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
289 286 0014 0003 |.CSBAR1 DC.W RAM/256+B64K CS1 base & option register values
290 287 0016 3830 |.CSOR1 DC.W 0*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
291 288 0018 0103 |.CSBAR2 DC.W RAM2/256+B64K CS2 base & option register values
292 289 001A 6870 |.CSOR2 DC.W 1*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
293 290 001C 0103 |.CSBAR3 DC.W RAM2/256+B64K CS3 base & option register values
294 291 001E 3030 |.CSOR3 DC.W 0*CS_WAIT+CS_LOWB+CS_W+CS_AS+CS_SUSP
295 292 0020 1004 |.CSBAR4 DC.W ROM2/256+B128K CS4 base & option register values
296 293 0022 5870 |.CSOR4 DC.W 1*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
297 294 0024 1004 |.CSBAR5 DC.W ROM2/256+B128K CS5 base & option register values
298 295 0026 3870 |.CSOR5 DC.W 1*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
299 296 0028 FFE8 |.CSBAR6 DC.W FPCP/256+B2K CS6 base & option register values
300 297 002A 783F |.CSOR6 DC.W CS_EXT+CS_BOTHB+CS_RW+CS_AS+CS_SUSP
301 298 002C 0000 |.CSBAR7 DC.W CSBAR_XX CS7 base & option register values
302 299 002E 0000 |.CSOR7 DC.W CSOR_XX . -- unused --
303 300 0030 FFF8 |.CSBAR8 DC.W AVEC_7/256 CS8 base & option register values
304 301 0032 680F |.CSOR8 DC.W 0*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_CSP+7*CS_LVL+CS_AVEC
305 302 0034 0000 |.CSBAR9 DC.W CSBAR_XX CS9 base & option register values
306 303 0036 0000 |.CSOR9 DC.W CSOR_XX . -- unused --
307 304 0038 0103 |.CSBAR10 DC.W RAM2/256+B64K CS10 base & option register values
308 305 003A 5030 |.CSOR10 DC.W 0*CS_WAIT+CS_UPPB+CS_W+CS_AS+CS_SUSP
309 306 |
310 307 |*----------------------------------------------------------------------------
311 308 |* Common Chip Select Table: (Rev. A BCC + Rev. A PFB) & (Rev. B BCC + Rev. B PFB)
312 309 |*
313 310 003C 0E04 |.CSBARBT DC.W ROM/256+B128K CSBOOT base & option register values
314 311 003E 68B0 |.CSORBT DC.W 2*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
315 312 |* - "2*CS_WAIT" = 2 wait cycles = AMD 27C1024-205LC 200 ns EPROM
316 313 |* This EPROM is 2 wait cycles because it is always enabled, whereas the
317 314 |* EPROM on the platform board (PFB) must first be enabled so it requires
318 315 |* 3 wait cycles!
319 316 |
320 317 |*----------------------------------------------------------------------------
321 318 |* New Chip Select Table: (Rev. B BCC + Rev. B PFB, or later!)
322 319 |*
323 320 0040 0003 |CSBAR0$ DC.W RAM/256+B64K CS0 base & option register values
324 321 0042 503E |CSOR0$ DC.W CS_FAST+CS_UPPB+CS_W+CS_AS+CS_SUSP
325 322 0044 0003 |CSBAR1$ DC.W RAM/256+B64K CS1 base & option register values
326 323 0046 303E |CSOR1$ DC.W CS_FAST+CS_LOWB+CS_W+CS_AS+CS_SUSP
327 324 0048 0003 |CSBAR2$ DC.W RAM/256+B64K CS2 base & option register values
328 325 004A 683E |CSOR2$ DC.W CS_FAST+CS_BOTHB+CS_R+CS_AS+CS_SUSP
329 326 004C 0000 |CSBAR3$ DC.W CSBAR_XX CS3 base & option register values
330 327 004E 0000 |CSOR3$ DC.W CSOR_XX . -- unused --
331 328 0050 FFF8 |CSBAR4$ DC.W AVEC_7/256 CS4 base & option register values
332 329 0052 680F |CSOR4$ DC.W 0*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_CSP+7*CS_LVL+CS_AVEC
333 330 0054 FFE8 |CSBAR5$ DC.W FPCP/256+B2K CS5 base & option register values
334 331 0056 783F |CSOR5$ DC.W CS_EXT+CS_BOTHB+CS_RW+CS_AS+CS_SUSP
335 332 0058 1004 |CSBAR6$ DC.W ROM2/256+B128K CS6 base & option register values
336 333 005A 38F0 |CSOR6$ DC.W 3*CS_WAIT+CS_LOWB+CS_RW+CS_AS+CS_SUSP
337 334 005C 1004 |CSBAR7$ DC.W ROM2/256+B128K CS7 base & option register values
338 335 005E 58F0 |CSOR7$ DC.W 3*CS_WAIT+CS_UPPB+CS_RW+CS_AS+CS_SUSP
339 336 0060 0103 |CSBAR8$ DC.W RAM2/256+B64K CS8 base & option register values
340 337 0062 6870 |CSOR8$ DC.W 1*CS_WAIT+CS_BOTHB+CS_R+CS_AS+CS_SUSP
341 338 0064 0103 |CSBAR9$ DC.W RAM2/256+B64K CS9 base & option register values
342 339 0066 3030 |CSOR9$ DC.W 0*CS_WAIT+CS_LOWB+CS_W+CS_AS+CS_SUSP
343 340 0068 0103 |CSBAR10$ DC.W RAM2/256+B64K CS10 base & option register values
344 341 006A 5030 |CSOR10$ DC.W 0*CS_WAIT+CS_UPPB+CS_W+CS_AS+CS_SUSP
345 342 |
346 343 |
347 344 |* The next two words are used to modify the Module Configuration Register (MCR)
348 345 |* per the formula shown below ( "[X]" = contents of location "X"):
349 346 |* MCR = ([MCR].OR.[MCR_OR]).AND.[MCR_AND]
350 347 |* Thus the power-on value of MCR is read, or'ed with MCR_OR, then and'ed with
351 348 |* MCR_AND, and then stored back into MCR. This allows us to modify the default
352 349 |* power-on value of MCR by adding bits we want and deleting bits we don't want!
353 350 |* This process allows the user to remap the internal registers, since the MM bit
354 351 |* is a write-once entity.
355 352 |*
356 353 006C 020F |MCR_OR DC.W $020F Show cycles enabled, external arbitration
357 354 |* enable, interrupt arbitration level = $F
358 355 |* (highest priority).
359 356 006E DFFF |MCR_AND DC.W $DFFF Enable bus monitor when FREEZE is asserted.
360 357 |* and set Module Mapping (MM) to map internal
361 358 |* modules to $FFF000-$FFFFFF.
362 359 |*MCR_AND DC.W $DFBF Enable bus monitor when FREEZE is asserted
363 360 |* and set Module Mapping (MM) to map internal
364 361 |* modules to $7FF000-$7FFFFF.
365 362 |
366 363 0070 06 |SYPCR_OR DC.B $06 Bus Monitor External Enabled, 16 system clocks
367 364 0071 7F |SYPCR_AND DC.B $7F Disable Software Watchdog
368 365 |*SYPCR_AND DC.B $FF Enable Software Watchdog
369 366 |
370 367 0072 8000 |FCRYSTAL DC.W FCRYSTVAL Crystal frequency (in Hz)
371 368 |
372 369 0074 FFFF FFFF |FEXTAL DC.L FILL.4 External clock frequency (in Hz)
373 370 |
374 371 |
375 372 |* ROM Auto Boot Vectors
376 373 0078 FFFF FFFF |RB_SP DC.L FILL.4 Allocate space for ROM BOOT SP and PC.
377 374 007C FFFF FFFF |RB_PC DC.L FILL.4!1 . PC bit0= 1 disables ROM BOOT!
378 375 0000 0000 | IFNE 4-(RB_PC-RB_SP)
379 376 | FAIL 469 ROM BOOT SP/PC not adjacent anymore!
380 377 | ENDC
381 378 |
382 379 |* SCI Console Default Initialization Table (CONSCI)
383 380 |*
384 381 0080 |CONSCI DS 0 * USE THIS FOR CONNECTION TO TERMINALS
385 382 |*
386 383 |******** Each bit set in '.PARMS' below enables the 7 parameters **********
387 384 |******** that follow. DO NOT ALTER THE VALUE OF '.PARAMS' below! **********
388 385 |*
389 386 0080 0000 1C0F |.PARMS DC.L $1C0F
390 387 |*
391 388 0084 2580 |.BAUD DC.W 9600 Baud rate (in decimal)
392 389 0086 00 |.PARITY DC.B 0 Parity: $00= none, 'E'= even, 'O'= odd
393 390 0087 08 |.DATA DC.B 8 Nbr. data bits: 7 or 8
394 391 0088 01 |.STOP DC.B 1 Nbr. stop bits: 1 or 2
395 392 0089 FF |.XON_ENB DC.B $FF XON/XOFF enable:
396 393 |* . $FF= enabled, $00= disabled
397 394 008A 11 |.XON DC.B $11 XON char: ^Q = $11
398 395 008B 13 |.XOFF DC.B $13 XOFF char: ^S = $13
399 396 |*
400 397 |
401 398 |* Periodic Interrupt Timer
402 399 |* - assumes 32.768 KHz clock
403 400 |*
404 401 008C 0642 |.PICR DC.W TIMERLVL<<8+TIMERVEC Periodic int. control reg. value
405 402 |* . Defines interrupt level & vector.
406 403 008E 0102 |.PITR DC.W $0102 Periodic int. timing reg. value
407 404 |* . Defines SYSCALL "tick" = 125 msec
408 405 |
409 406 |* Power On Branch Vectors
410 407 |* - There are no entry/exit restrictions for register usage here.
411 408 |*
412 409 |PWR_ON:
413 410 0090 60FF FFFF |PWR_TBL1 BRA.L INIT_T1 Table #1 Initialization processing
413 0094 FF6E |
414 411 |* . - returns [A6]= Init Table #2 start addr
415 412 |* . - returns to PWR_INI
416 413 0096 60FF FFFF |PWR_INI BRA.L INIT_CS Initialize chip selects, etc. for 68332
416 009A FF68 |
417 414 |* . - returns [D7.L]= Power Up Status Flag
418 415 |* . - preserves [A6]
419 416 |* . - returns to PWR_TBL2
420 417 009C 60FF FFFF |PWR_TBL2 BRA.L INIT_T2 Table #2 Initialization processing
420 00A0 FF62 |
421 418 |* . - entry [A6]= Init Table #2 start addr
422 419 |* . - preserves [D7]
423 420 |* . - returns to PWR_TTL
424 421 00A2 60FF 0000 |PWR_TTL BRA.L PWR_TST Print sign on message title.
424 00A6 0004 |
425 422 |* . - preserves [D7]
426 423 |* . - returns to PWR_TST
427 424 |* NOTE: PWR_TTL is not enabled yet. Signon message actually gets printed
428 425 |* in SYSINIT routine via TRAP 15 calls! This may be changed in the
429 426 |* future so simple SCI routines w/o stack usage can print messages
430 427 |* until system has been verified (use address regs for return addrs).
431 428 |*
432 429 00A8 60FF FFFF |PWR_TST BRA.L CONFTST Perform confidence tests.
432 00AC FF56 |
433 430 |* . - preserves [D7.L bits 8-31]
434 431 |* . - returns [D7.B]= error code flag
435 432 |* . - returns to PWR_GO
436 433 00AE 60FF FFFF |PWR_GO BRA.L SYSINIT Go start up the system.
436 00B2 FF50 |
437 434 |* . - entry [D7.L bits 8-31]= Power Up
438 435 |* . Status Flag
439 436 |* . - entry [D7.B]= self-test error code flag
440 437 |* . - never returns
441 438 00B4 FFFF FFFF | DCB.W 2*3,FILL.2 Reserve space for 2 more BRA.L's (3 words each)
441 438 00B8 FFFF FFFF |
442 439 0000 00C0 |PWR_END EQU *
443 440 |
444 441 00C0 FFFF FFFF | DCB.B 16,FILL.1 <reserved>
444 441 00C4 FFFF FFFF |
445 442 |
446 443 |* Initialization Table Area:
447 444 |* - see INITTBL.SA for description!
448 445 |*
449 446 00D0 FFFF FFFF |INITTBL DCB.B $A0,FILL.1
449 446 00D4 FFFF FFFF |
450 447 0000 0170 |INITTBLE EQU * End of Init. Table.
451 448 |
452 449 |* Sign On Message Test String
453 450 |*
454 451 0170 |SIGNON DS.W 0
455 452 0170 8F | DC.B SIGN$2-SIGN$1 Set msg byte count
456 453 0171 0D0A 0A |SIGN$1 DC.B CR,LF,LF
457 454 0174 4350 5533 |SIGN$3 DC.B 'CPU32Bug Debugger/Diagnostics - Version 1.00'
457 454 0178 3242 7567 |
457 454 017C 2044 6562 |
457 454 0180 7567 6765 |
457 454 0184 722F 4469 |
457 454 0188 6167 6E6F |
457 454 018C 7374 6963 |
457 454 0190 7320 2D20 |
457 454 0194 5665 7273 |
457 454 0198 696F 6E20 |
457 454 019C 2031 2E30 |
457 454 01A0 30 |
458 455 0000 002D |SIGN1SZ EQU *-SIGN$3 # chars in line #1 = $2D= 45
459 456 01A1 2020 2020 | DCB.B 34,SPACE Pad to end of line (79-45= 34)
459 456 01A5 2020 2020 |
460 457 01C3 0D0A | DC.B CR,LF
461 458 01C5 2028 4329 |SIGN$4 DC.B ' (C) Copyright 1991 by Motorola Inc.'
461 458 01C9 2043 6F70 |
461 458 01CD 7972 6967 |
461 458 01D1 6874 2031 |
461 458 01D5 3939 3120 |
461 458 01D9 6279 204D |
461 458 01DD 6F74 6F72 |
461 458 01E1 6F6C 6120 |
461 458 01E5 496E 632E |
462 459 0000 0024 |SIGN2SZ EQU *-SIGN$4 # chars in line #2 = $24= 36
463 460 0000 0017 |SIGN3SZ EQU ($200-(SIGNON-ORIGIN))-(*-SIGNON) Extra space= $17 = 23
464 461 01E9 2020 2020 | DCB.B 23,SPACE Pad to end of sigon space
464 461 01ED 2020 2020 |
465 462 0000 0200 |SIGN$2 EQU *
466 463 |
467 464 0000 0000 | IFNE $200-(*-ORIGIN)
468 465 | FAIL 499 Param area must= $200 to match user documentation!
469 466 | ENDC
470 467 0000 0000 | IFNE $08-(CODESIZE-ORIGIN)
471 468 | FAIL 499 CODESIZE must= offset $08 to match user documentation!
472 469 | ENDC
473 470 0000 0000 | IFNE $0C-(SRECMAX-ORIGIN)
474 471 | FAIL 499 SRECMAX must= offset $0C to match user documentation!
475 472 | ENDC
476 473 0000 0000 | IFNE $0E-(CHECKSUM-ORIGIN)
477 474 | FAIL 499 CHECKSUM must= offset $0E to match user documentation!
478 475 | ENDC
479 476 0000 0000 | IFNE $10-(.CSBAR0-ORIGIN)
480 477 | FAIL 499 .CSBAR0 must= offset $10 to match user documentation!
481 478 | ENDC
482 479 0000 0000 | IFNE $12-(.CSOR0-ORIGIN)
483 480 | FAIL 499 .CSOR0 must= offset $12 to match user documentation!
484 481 | ENDC
485 482 0000 0000 | IFNE $3C-(.CSBARBT-ORIGIN)
486 483 | FAIL 499 .CSBARBT must= offset $3C to match user documentation!
487 484 | ENDC
488 485 0000 0000 | IFNE $3E-(.CSORBT-ORIGIN)
489 486 | FAIL 499 .CSORBT must= offset $3E to match user documentation!
490 487 | ENDC
491 488 0000 0000 | IFNE $40-(CSBAR0$-ORIGIN)
492 489 | FAIL 499 CSBAR0$ must= offset $40 to match user documentation!
493 490 | ENDC
494 491 0000 0000 | IFNE $42-(CSOR0$-ORIGIN)
495 492 | FAIL 499 CSOR0$ must= offset $42 to match user documentation!
496 493 | ENDC
497 494 0000 0000 | IFNE $6C-(MCR_OR-ORIGIN)
498 495 | FAIL 499 MCR_OR must= offset $6C to match user documentation!
499 496 | ENDC
500 497 0000 0000 | IFNE $6E-(MCR_AND-ORIGIN)
501 498 | FAIL 499 MCR_AND must= offset $6E to match user documentation!
502 499 | ENDC
503 500 0000 0000 | IFNE $70-(SYPCR_OR-ORIGIN)
504 501 | FAIL 499 SYPCR_OR must= offset $70 to match user documentation!
505 502 | ENDC
506 503 0000 0000 | IFNE $71-(SYPCR_AND-ORIGIN)
507 504 | FAIL 499 SYPCR_AND must= offset $71 to match user documentation!
508 505 | ENDC
509 506 0000 0000 | IFNE $72-(FCRYSTAL-ORIGIN)
510 507 | FAIL 499 FCRYSTAL must= offset $72 to match user documentation!
511 508 | ENDC
512 509 0000 0000 | IFNE $74-(FEXTAL-ORIGIN)
513 510 | FAIL 499 FEXTAL must= offset $74 to match user documentation!
514 511 | ENDC
515 512 0000 0000 | IFNE $78-(RB_SP-ORIGIN)
516 513 | FAIL 499 RB_SP must= offset $78 to match user documentation!
517 514 | ENDC
518 515 0000 0000 | IFNE $7C-(RB_PC-ORIGIN)
519 516 | FAIL 499 RB_PC must= offset $7C to match user documentation!
520 517 | ENDC
521 518 0000 0000 | IFNE $80-(.PARMS-ORIGIN)
522 519 | FAIL 499 .PARMS must= offset $80 to match user documentation!
523 520 | ENDC
524 521 0000 0000 | IFNE $84-(.BAUD-ORIGIN)
525 522 | FAIL 499 .BAUD must= offset $84 to match user documentation!
526 523 | ENDC
527 524 0000 0000 | IFNE $86-(.PARITY-ORIGIN)
528 525 | FAIL 499 .PARITY must= offset $86 to match user documentation!
529 526 | ENDC
530 527 0000 0000 | IFNE $87-(.DATA-ORIGIN)
531 528 | FAIL 499 .DATA must= offset $87 to match user documentation!
532 529 | ENDC
533 530 0000 0000 | IFNE $88-(.STOP-ORIGIN)
534 531 | FAIL 499 .STOP must= offset $88 to match user documentation!
535 532 | ENDC
536 533 0000 0000 | IFNE $89-(.XON_ENB-ORIGIN)
537 534 | FAIL 499 .XON_ENB must= offset $89 to match user documentation!
538 535 | ENDC
539 536 0000 0000 | IFNE $8A-(.XON-ORIGIN)
540 537 | FAIL 499 .XON must= offset $8A to match user documentation!
541 538 | ENDC
542 539 0000 0000 | IFNE $8B-(.XOFF-ORIGIN)
543 540 | FAIL 499 .XOFF must= offset $8B to match user documentation!
544 541 | ENDC
545 542 0000 0000 | IFNE $8C-(.PICR-ORIGIN)
546 543 | FAIL 499 .PICR must= offset $8C to match user documentation!
547 544 | ENDC
548 545 0000 0000 | IFNE $8E-(.PITR-ORIGIN)
549 546 | FAIL 499 .PITR must= offset $8E to match user documentation!
550 547 | ENDC
551 548 0000 0000 | IFNE $90-(PWR_ON-ORIGIN)
552 549 | FAIL 499 PWR_ON must= offset $90 to match user documentation!
553 550 | ENDC
554 551 0000 0000 | IFNE $90-(PWR_TBL1-ORIGIN)
555 552 | FAIL 499 PWR_TBL1 must= offset $90 to match user documentation!
556 553 | ENDC
557 554 0000 0000 | IFNE $96-(PWR_INI-ORIGIN)
558 555 | FAIL 499 PWR_INI must= offset $96 to match user documentation!
559 556 | ENDC
560 557 0000 0000 | IFNE $9C-(PWR_TBL2-ORIGIN)
561 558 | FAIL 499 PWR_TBL2 must= offset $9C to match user documentation!
562 559 | ENDC
563 560 0000 0000 | IFNE $A2-(PWR_TTL-ORIGIN)
564 561 | FAIL 499 PWR_TTL must= offset $A2 to match user documentation!
565 562 | ENDC
566 563 0000 0000 | IFNE $A8-(PWR_TST-ORIGIN)
567 564 | FAIL 499 PWR_TST must= offset $A8 to match user documentation!
568 565 | ENDC
569 566 0000 0000 | IFNE $AE-(PWR_GO-ORIGIN)
570 567 | FAIL 499 PWR_GO must= offset $AE to match user documentation!
571 568 | ENDC
572 569 0000 0000 | IFNE $D0-(INITTBL-ORIGIN)
573 570 | FAIL 499 INITTBL must= $D0 to match user documentation!
574 571 | ENDC
575 572 0000 0000 | IFNE $170-(INITTBLE-ORIGIN)
576 573 | FAIL 499 INITTBLE must= $170 to match user documentation!
577 574 | ENDC
578 575 0000 0000 | IFNE $170-(SIGNON-ORIGIN)
579 576 | FAIL 499 SIGNON must= $170 to match user documentation!
580 577 | ENDC
581 578 |
582 579 | END
582 lines assembled
symbol table:
symbol name attrib. section value
----------- ------- ------- -----
ORIGIN .data 8 0x0
578 575 572 569 566 563 560 557 554 551
548 545 542 539 536 533 530 527 524 521
518 515 512 509 506 503 500 497 494 491
488 485 482 479 476 473 470 467 463 @267
@58
CODESIZE .data 8 0x8
470 @271 @59
CHECKSUM .data 8 0xe
476 @276 @60
.CSBAR0 .data 8 0x10
479 @287 @62
.CSBAR1 .data 8 0x14
@289 @62
.CSBAR2 .data 8 0x18
@291 @62
.CSBAR3 .data 8 0x1c
@293 @62
.CSBAR4 .data 8 0x20
@295 @62
.CSBAR5 .data 8 0x24
@297 @62
.CSBAR6 .data 8 0x28
@299 @63
.CSBAR7 .data 8 0x2c
@301 @63
.CSBAR8 .data 8 0x30
@303 @63
.CSBAR9 .data 8 0x34
@305 @63
.CSBAR10 .data 8 0x38
@307 @63
.CSOR0 .data 8 0x12
482 @288 @65
.CSOR1 .data 8 0x16
@290 @65
.CSOR2 .data 8 0x1a
@292 @65
.CSOR3 .data 8 0x1e
@294 @65
.CSOR4 .data 8 0x22
@296 @65
.CSOR5 .data 8 0x26
@298 @65
.CSOR6 .data 8 0x2a
@300 @66
.CSOR7 .data 8 0x2e
@302 @66
.CSOR8 .data 8 0x32
@304 @66
.CSOR9 .data 8 0x36
@306 @66
.CSOR10 .data 8 0x3a
@308 @66
.CSBARBT .data 8 0x3c
485 @313 @68
.CSORBT .data 8 0x3e
488 @314 @69
CSBAR0$ .data 8 0x40
491 @323 @71
CSBAR1$ .data 8 0x44
@325 @71
CSBAR2$ .data 8 0x48
@327 @71
CSBAR3$ .data 8 0x4c
@329 @71
CSBAR4$ .data 8 0x50
@331 @71
CSBAR5$ .data 8 0x54
@333 @71
CSBAR6$ .data 8 0x58
@335 @72
CSBAR7$ .data 8 0x5c
@337 @72
CSBAR8$ .data 8 0x60
@339 @72
CSBAR9$ .data 8 0x64
@341 @72
CSBAR10$ .data 8 0x68
@343 @72
CSOR0$ .data 8 0x42
494 @324 @74
CSOR1$ .data 8 0x46
@326 @74
CSOR2$ .data 8 0x4a
@328 @74
CSOR3$ .data 8 0x4e
@330 @74
CSOR4$ .data 8 0x52
@332 @74
CSOR5$ .data 8 0x56
@334 @74
CSOR6$ .data 8 0x5a
@336 @75
CSOR7$ .data 8 0x5e
@338 @75
CSOR8$ .data 8 0x62
@340 @75
CSOR9$ .data 8 0x66
@342 @75
CSOR10$ .data 8 0x6a
@344 @75
MCR_OR .data 8 0x6c
497 @356 @77
MCR_AND .data 8 0x6e
500 @359 @78
.PICR .data 8 0x8c
545 @404 @79
.PITR .data 8 0x8e
548 @406 @80
RB_SP .data 8 0x78
515 378 @376 @81
RB_PC .data 8 0x7c
518 378 @377 @82
CONSCI .data 8 0x80
@384 @83
.PARMS .data 8 0x80
521 @389 @84
.BAUD .data 8 0x84
524 @391 @85
.PARITY .data 8 0x86
527 @392 @86
.DATA .data 8 0x87
530 @393 @87
.STOP .data 8 0x88
533 @394 @88
.XON_ENB .data 8 0x89
536 @395 @89
.XON .data 8 0x8a
539 @397 @90
.XOFF .data 8 0x8b
542 @398 @91
SYPCR_OR .data 8 0x70
503 @366 @92
SYPCR_AND .data 8 0x71
506 @367 @93
FEXTAL .data 8 0x74
512 @372 @94
FCRYSTAL .data 8 0x72
509 @370 @95
PWR_ON .data 8 0x90
551 @412 269 @96
PWR_TBL1 .data 8 0x90
554 @413 @97
PWR_INI .data 8 0x96
557 @416 @98
PWR_TBL2 .data 8 0x9c
560 @420 @99
PWR_TTL .data 8 0xa2
563 @424 @100
PWR_TST .data 8 0xa8
566 @432 424 @101
PWR_GO .data 8 0xae
569 @436 @102
INITTBL .data 8 0xd0
572 @449 @103
INITTBLE .data 8 0x170
575 @450 @104
SIGNON .data 8 0x170
578 463 463 @454 @105
CONFTST xref
432 @109
SYSINIT xref
436 @110
INIT_CS xref
416 @111
INIT_T1 xref
413 @112
INIT_T2 xref
420 @113
MEMPAGE xref
@114
VECTOR macro
262
CR abs. 0xd
460 456 @127
LF abs. 0xa
460 456 456 @128
SPACE abs. 0x20
464 459 @129
SR_VAL abs. 0x2700
@137
RAM_BASE abs. 0x0
197 159 @139
RAM_SIZE abs. 0x10000
161 @140
ROM1_BASE abs. 0xe0000
198 174 166 @141
ROM1_SIZE abs. 0x20000
271 174 @142
IRAM_BASE abs. 0x40000
202 @143
FPCP_BASE abs. 0xffffe800
201 @144
FCRYSTVAL abs. 0x8000
370 @146
HI_BASE abs. 0xfffff000
@147
LO_BASE abs. 0x7ff000
@149
SIM abs. 0xa00
@150
RAMCR abs. 0xb00
@151
QSM abs. 0xc00
@152
AUTO_BASE abs. 0xfffff800
203 @153
EXTAL_BIT abs. 0x1f
@156
CHKSUM_BIT abs. 0x1e
@157
LOCALRAM abs. 0x0
268 173 164 162 @159
SYSRAMSZ abs. 0x4000
163 162 @160
LCLRAMMX abs. 0x10000
173 163 @161
USRRAM abs. 0x4000
@162
USRRAMSZ abs. 0xc000
@163
RAMSTART abs. 0x0
@164
LOCALROM abs. 0xe0000
@166
LCLROMSZ abs. 0x10000
@167
ROMUNPGM abs. 0xff
169 @168
FILL.1 abs. 0xff
449 444 275 170 170 @169
FILL.2 abs. 0xffff
441 171 171 @170
FILL.4 abs. 0xffffffff
377 376 372 @171
RAM2_BASE abs. 0x10000
199 @173
ROM2_BASE abs. 0x100000
200 @174
VECTSIZ abs. 0x400
268 179 @176
USERLEN abs. 0x1000
179 @177
MEMINC abs. 0x4000
179 @178
STKLEN abs. 0x2bfc
268 @179
ABORTLVL abs. 0x7
@184
ABORTVEC abs. 0x1f
@185
ACFAILVL abs. 0x7
@186
ACFAILVC abs. 0x41
@187
TIMERLVL abs. 0x6
404 @188
TIMERVEC abs. 0x42
404 @189
ADDRMASK abs. 0xfff800
203 202 201 200 199 198 197 @196
RAM abs. 0x0
327 325 323 289 287 @197
ROM abs. 0xe0000
313 @198
RAM2 abs. 0x10000
343 341 339 307 293 291 @199
ROM2 abs. 0x100000
337 335 297 295 @200
FPCP abs. 0xffe800
333 299 @201
IRAM abs. 0x40000
@202
AVEC_7 abs. 0xfff800
331 303 @203
CSBAR_XX abs. 0x0
329 305 301 @205
CSOR_XX abs. 0x0
330 306 302 @206
B2K abs. 0x0
333 299 @211
B8K abs. 0x1
@212
B16K abs. 0x2
@213
B64K abs. 0x3
343 341 339 327 325 323 307 293 291 289
287 @214
B128K abs. 0x4
337 335 313 297 295 @215
B256K abs. 0x5
@216
B512K abs. 0x6
@217
B1M abs. 0x7
@218
ASYNC abs. 0x0
@219
SYNC abs. 0x8000
@220
CS_UPPB abs. 0x4000
344 338 324 308 296 288 @221
CS_LOWB abs. 0x2000
342 336 326 298 294 290 @222
CS_BOTHB abs. 0x6000
340 334 332 328 314 304 300 292 @223
CS_R abs. 0x800
340 332 328 314 304 292 @224
CS_W abs. 0x1000
344 342 326 324 308 294 @225
CS_RW abs. 0x1800
338 336 334 300 298 296 290 288 @226
CS_AS abs. 0x0
344 342 340 338 336 334 332 328 326 324
314 308 304 300 298 296 294 292 290 288
@227
CS_DS abs. 0x400
@228
CS_FAST abs. 0xe
328 326 324 @229
CS_EXT abs. 0xf
334 300 @230
CS_WAIT abs. 0x40
344 342 340 338 336 332 314 308 304 298
296 294 292 290 288 @231
CS_CSP abs. 0x0
332 304 @232
CS_USP abs. 0x10
@233
CS_SSP abs. 0x20
@234
CS_SUSP abs. 0x30
344 342 340 338 336 334 328 326 324 314
308 300 298 296 294 292 290 288 @235
CS_LVL abs. 0x2
332 304 @236
CS_AVEC abs. 0x1
332 304 @237
CHECKVAL abs. 0x3033
276 @244
SECTD abs. 0x0
@263
SECTP abs. 0x8
265 @264
PWR_SSP .data 8 0x0
@268
PWR_PC .data 8 0x4
@269
SRECMAX .data 8 0xc
473 @272
CHECKALT .data 8 0xd
@275
PWR_END .data 8 0xc0
@442
SIGN$2 .data 8 0x200
@465 455
SIGN$1 .data 8 0x171
@456 455
SIGN$3 .data 8 0x174
458 @457
SIGN1SZ abs. 0x2d
@458
SIGN$4 .data 8 0x1c5
462 @461
SIGN2SZ abs. 0x24
@462
SIGN3SZ abs. 0x17
@463
.data section 8 0x0
181 symbols